1. Field of the Invention
The present invention relates to a memory device provided with direct sense circuits and a plurality of semi-parallelly accessible memory blocks such as a synchronous dynamic random access memory (SDRAM) with multi-banks and a semiconductor device having the same.
2. Description of the Related Art
FIG. 18 shows a schematic layout pattern of the core part of a prior art. The core part is provided with banks 0 through 3 for a high speed processing with semi-parallel operations. A bank address, a block address and a row address from the outside is predecoded by a predecoder 10, it is further decoded by a word decoder 11, and for example, one row in the memory block, of a bank 0, formed between rows 12A and 12B of sense circuits including sense amplification circuits, etc., is selected with a word line WL. The memory content on this row is read out on a bit line and is amplified by the sense circuit rows 12A and 12B. More concretely, for example, the memory content of a memory cell 14 is read out on a bit line BL and is amplified by a sense amplification circuit 122 in the sense circuit row 12B. A column address from the outside is decoded by a column decoder 13A, and for example, a column gate selected in the sense circuit row 12B turns on by a column selection line CL, whereby the data on the bit line BL is read out onto a local data bus LDB, further on to a global data bus GDB and is amplified in the sense buffer circuit 15A.
However, it is necessary to provide column decoders 13A through 13D in the banks 0 through 3, respectively. Further, it is necessary to provide a sense buffer circuit 15B disposed between the bank 1 and bank 3 in addition to the sense buffer circuit 15A disposed between the bank 0 and bank 2. Therefore, the chip area is increased or the storage capacity is suppressed. Furthermore, since it is necessary to form address lines from an address buffer register to each of the column decoders 13A through 13D, the operation speed is decreased.
FIG. 19 shows the first improvement on FIG. 18 to solve these problems.
In the core part, banks 0 through 3 are disposed in a column, and a column decoder 13 and a sense buffer circuit 15 are disposed so that the banks 0 through 3 are placed therebetween. Column gates of the same column of the banks 0 through 3 are simultaneously selected with a column selection line CL connected to the output of the column decoder 13. If a global data bus GDB is made common for the banks 0 through 3, data on the global data bus GDB are brought into collision with each other when a plurality of banks are activated at the same time. Therefore, the global data bus GDB is provided for each of the banks and it is necessary that each global data bus is connected to the sense buffer circuit 15. Further, since a longer global data bus GDB than that in the case of FIG. 18 is used for each of a plurality of banks operating in semi-parallel, consumption power is increased.
FIG. 20 shows the second improvement in which a global data bus GDB is made common for banks 0 through 3.
In this case, in order that data are read out from a plurality of activated banks in time sharing and are not brought into collision with each other on the global data bus GDB, as regards each column of the banks 0 through 3, it is necessary to provide an independent column selection line CL for each of the banks. Therefore, the wiring pitch of the column selection line CL becomes one-fourth that of the prior art, such shortcomings as short-circuit between wires are likely to occur. If it is attempted to avoid this, the chip area is increased.
In order to solve these shortcomings, as shown in FIG. 21, if column decoders 13A through 13D are provided for each of the banks 0 through 3, the pattern becomes similar to that of the prior art structure of FIG. 18.